The present invention relates generally to semiconductor dies and their fabrication and, more particularly, to analysis of semiconductor dies involving capacitive probing.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages.
A by-product of such high-density and high functionality is an increased demand for products employing these microprocessors and devices for use in numerous applications. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased. Such devices often require manufacturing processes that are highly complex and expensive.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
Traditionally, integrated circuits have been tested using methods including directly accessing circuitry or devices within the integrated circuit. Directly accessing the circuitry is difficult for several reasons. For instance, in flip-chip type dies, transistors and other circuitry are located in a very thin epitaxially grown silicon layer in a circuit side of the die. The circuit side of the die is arranged facedown on a package substrate. This orientation provides many operational advantages. However, due to the facedown orientation of the circuit side of the die, the transistors and other circuitry near the circuit side are not readily accessible for testing, modification, or other purposes. Therefore, access to the transistors and circuitry near the circuit side is from the back side of the die.
One particular type of semiconductor device structure that presents unique challenges to back side circuit analysis is silicon-on-insulator (SOI) structure. SOI involves forming an insulator, such as an oxide, over bulk silicon in the back side of a semiconductor device. A thin layer of silicon is formed on top of the insulator, and is used to form circuitry over the insulator. The resulting SOI structure exhibits benefits including reduced switch capacitance, which leads to faster operation. Direct access to circuitry for analysis of SOI structure, however, involves milling through the oxide. The milling process can damage circuitry or other structure in the device. Such damage can alter the characteristics of the device and render the analysis inaccurate. In addition, the milling process can be time-consuming, difficult to control, and thus expensive.
The difficulty, cost, and destructive aspects of existing methods for testing integrated circuits are impediments to the growth and improvement of semiconductor technologies involving SOI structure.
The present invention is directed to a method and system for analyzing a semiconductor die having silicon-on-insulator (SOI) structure in a manner that addresses and can even overcome the above-discussed impediments. The die includes a back side opposite circuitry in a circuit side, and the die analysis involves coupling to determine the static logic state of the circuitry. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor die having SOI structure and a back side opposite circuitry in a circuit side is analyzed. A portion of substrate is removed from the back side of the semiconductor die and an exposed region of the insulator portion of the SOI die is formed. A detectable response is induced from the exposed region as a function of a static logic state of a portion of the circuitry. Detecting a response from the die in this manner expedites and enhances analysis of semiconductor devices that employ SOI construction, thereby improving the manufacture, testing, and technological advancement of such devices.
In another example embodiment of the present invention, an electron beam is directed at the exposed region in the semiconductor die using, for example, a scanning electron microscope (SEM). The electron beam generates secondary electrons in the exposed region that are detected and used to analyze the die. Such generation of secondary electrons occurs as a finction of an electrical characteristic, such as a logic state, of a portion of the circuitry in the die. This functional relationship between the generation of secondary electrons and the electrical characteristic of the circuitry is used to analyze the die.
According to another example embodiment of the present invention, a system is adapted to analyze a semiconductor die having silicon-on-insulator (SOI) structure and a back side opposite circuitry in a circuit side. The system includes a substrate removal arrangement adapted to remove substrate from the back side of the semiconductor die and form an exposed region in the insulator portion of the SOI structure. A probe arrangement is adapted to induce a detectable response from the exposed region as a function of the logic state of a portion of the circuitry. A detector is adapted to detect the response and to analyze the die therefrom.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.